The present invention relates to a semiconductor memory device with redundancy.
In the recent semiconductor memory devices with a high density integration and a large memory capacity, a variation in the manufacturing process or dust contained in air frequently provides an imperfect etching process, which increases bit errors in the memory. This results in deterioration of the production yield. In the case of the programmable read only memory (PROM) of the melting type, because of a variation in the working accuracy, the fuse fails to be melted, causing an bit error. In the case of the PROM of 4 Kbit, for example, a percentage of occurences of defective articles is about 5 to 10%.
To solve such write error problem, there is proposed a memory device which uses a redundancy circuit to rescue a read error based on the bit error. FIG. 1 shows a memory device with the redundancy circuit. In FIG. 1, reference numeral 1 designates a decoder circuit for decoding an address signal A.sub.R in a row direction; 2 a decoder circuit for decoding an address signal A.sub.C in a column direction; 3 a main memory (cell group) which is addressed by the address signals produced from the decoder circuits 1 and 2; 4 an auxiliary memory (cell group) providing a redundancy bits; 5 a switch for connecting or disconnecting a decode line connecting to the decoder circuit 1 and a word line connecting to the main memory 3; 6 a switch for connecting or disconnecting a decode line of the decoder circuit 1 and a word line connecting to the auxiliary memory 4; 7 a switch for selecting output data from the main memory and the output data from the auxiliary memory.
Let us consider the address signal A.sub.R in a row direction in the memory device constructed as such. The address signal A.sub.R is decoded by the row decoder 1 and is then applied into the word lines of the main memory 3 through the switch 5 being in an ON state (indicated by a solid line). A single word line, e.g. WL.sub.M, is selected on the basis of the contents of the row address signal A.sub.R. When an error bit or an incorrect bit is contained in any one of the main memory cells arranged on the word line WL.sub.M, the switch 5 is turned off, as indicated by a dotted line, to disconnect the decoder line DL.sub.M leading to the decoder circuit 1 from the word line WL.sub.M of the main memory 3. At the same time, the switch 6 is turned on, as indicated by a dotted line, to connect the decode line DL.sub.M to the word line WL.sub.A of the auxiliary memory 4. Through this switching operation, the memory cells 9 in the auxiliary memory 4 are selected. In this case, if any one of the memory cells 9 in the auxiliary memory 4 has no error bit, the main memory 3 having the bit error in the memory cell 8 is repaired.
The prior memory device of this type employs the same number of auxiliary memory cells as those of the main memory to repair the main memory cell respective of which word line or how many word lines contain the error bit cell or cells. The prior art further employs multiplexers complicated in construction and operation for the switches 5 to 7, as shown in FIG. 2.
There is another proposal of a semiconductor memory device with redundancy. The memory device employs a more complicated switch control system for the main and auxiliary memories having a further number of switches. However, in the memory device, the number of memory cells in the auxiliary memory is limited to that of the memory cells on one word line in the main memory. In this respect, the chip area occupied by the auxiliary memory is remarkable reduced, compared with the former prior art memory device.
The former memory device has infrequently been used because it needs substantially the chip area two times that of the memory device with no auxiliary memory. For this reason, the latter means has dominantly been used; however, it needs the auxiliary memory cells of which the number is the same as that of those on one row line, even if the error bit cell on the word line of the main memory 3 is one. Accordingly, the chip area necessary for the auxiliary memory is still large. Further, the switch control system is more complicated than the former prior art.